1. Field of the Invention
The present invention generally relates to design structures, and more particularly, design structures in the field of symmetric multiprocessing (SMP) systems and more particularly to cache line management for SMP systems.
2. Description of the Related Art
SMP systems refer generally to computing platforms having multiple processing units coupled to one another over a high speed bus. SMP systems have proven highly effective in the concurrent processing of computing tasks in order to accelerate computing performance for the system as a whole. SMP systems can range from the loosely coupled to the tightly coupled. In a loosely coupled SMP system, each processing unit stands alone and shares common memory and communications resources. Notably, in the loosely coupled system, each processing unit can handle any processing task. By comparison, in a tightly coupled SMP system, the processing units are grouped together and each processing unit can be designated a particular type of task.
Just as in the case of a single processing environment, in an SMP environment, data caching can have a dramatic impact on the speed at which processing tasks can be performed. In the SMP environment unlike the single processing environment, however, substantial challenges exist in the coordination and management of data caching across multiple data caches for multiple, different processing units. Coordinating and managing data caching across multiple data caches in order to ensure consistency among cache lines possibly accessed within different computing nodes has come to be referred to as the practice of cache coherence.
An SMP system generally employs a “snoopy” mechanism to ensure cache coherence. In operation, when a cache miss occurs, the requesting cache sends a cache request to main memory and to all of its peer caches. When a peer cache receives the cache request, the peer cache “snoops” its cache directory and produces a cache snoop response indicating whether the requested data is found and the state of the corresponding cache line. If the requested data is found in a peer cache, the peer cache can source the data to the requesting cache via a cache-to-cache transfer. The memory is responsible for supplying the requested data if the data cannot be supplied by any peer cache. In this way, cache coherence can be achieved by inspecting all caches in the SMP system before responding to a data request.
There are many techniques for achieving cache coherence that are known to those skilled in the art. A number of snoopy cache coherence protocols have been proposed including the Modified Exclusive Shared Invalid (MESI) coherence protocol. MESI defines four cache states: modified (M), exclusive (E), shared (S) and invalid (I). In the invalid state, associated data is not valid, whereas in the shared state, associated data is valid, and can also be valid in the caches of other nodes. The shared state is entered when the data is sourced from the memory or another cache in the modified state, and a corresponding snoop response shows that the data is valid in at least one of the other caches. In an exclusive state, associated data is valid, and has not been modified. Yet, the associated data is exclusively owned, and cannot be valid in another cache. The exclusive state is entered when the associated data is sourced from the memory or another cache in the modified state, and the corresponding snoop response shows that the data is not valid in another cache. Finally, in a modified state, associated data is valid and has been modified. Yet as before, the data is exclusively owned and cannot be valid in another cache.
In practice, in an SMP system a cache line requested for use by a peer cache in a local node can be managed as between the node controllers for the home node and local node corresponding to the peer caches. Normally, once a peer cache in a local node has obtained a copy of a cache line remotely, the requesting processor in the local node can utilize the cache line in the peer cache and eventually, the processor can drop the cache line resulting in a state transition for the cache line from exclusive to invalid, as it is well-known in the art.
In as much as the different node controllers for the different nodes in an SMP system do not communicate with one another, all of the node controllers excepting for the node controller for the local cache will remain oblivious to the occurrence of the silent invalid state transition for the cache line in a local node. Rather, only when a subsequent request for the cache line is processed by the node controller for the cache in the home node will the other node controllers become aware of the invalid state for the cache line. Consequently, substantial latencies can result and the local directories for the different node controllers will needlessly waste storage space storing an entry for the invalid cache line.